At last week’s Intel Architecture Day, Intel’s chief architect, Raja Koduri, briefly mentioned the smallest member of the company’s upcoming Xe-HP series of server CPUs, the single-tile configuration. Now, just a few days later, he has raised the ante by showing off the largest configuration of four tiles.
Designed to be a scalable chip architecture, Xe-HP is set to be available with one, two or four tiles. And although Intel has not yet revealed too much in the way of details about the architecture, based on its packaging information, it looks like the company is using its EMIB tech to upgrade the GPU tiles, such as HBU’s memory the GPU.
Assuming it makes it to market, a multi-tile GPU – essentially multiple GPUs in one package – would be a great achievement for Intel. GPUs are notoriously bandwidth hungry due to the need to shovel data between cores, caches, and command front ends, making them non-trivial to split in a chiplet / tiled manner. Even if Intel can only use this kind of multi-tile scalability for computed workloads, it would have a significant impact on what performance a single GPU package can achieve, and how future servers can be built.
