Following the current GPU news from Intel’s Architecture Day presentation, on top of the Xe – LP architecture briefing and Xe – HPG unveiling, the company also offered a brief update of the route map for its part of the flagship sever level, Xe-HPC.
Better known by its code name of Ponte Vecchio, much has been made about Xe-HPC. The most complex of the planned Xe parts, it is also the cornerstone of the Intel-powered Aurora supercomputer. Xe-HPC pulls up all the stops for performance, and to get there, Intel uses every trick in the book, including its new generation of advanced packaging technologies.
The big revelation here is that we finally have some concrete insight into what manufacturing processes the different tiles will use. The base tile of the GPU will be on Intel’s new 10nm SuperFin process, and the Rambo Cache will be a generation even newer, with Intel’s future 10nm Enhanced SuperFin process with Intel. Meanwhile, it has now been confirmed that the Xe Link I / O tile, which will be used as part of Intel’s fabric to connect multiple Xe-HPC GPUs together, will be built by an external fab.
That leaves the issue of the computer tile, the most performance-critical of the GPU parts. With Intel’s 7nm process delayed by at least six months, the company has previously announced that it will take a “pragmatic” approach and potentially use third-party factory. And since their Architecture Day update, they still seem undecided about – or at least not ready to reveal – exactly what they plan to do. Instead, the computing statistics are called “Intel Next Gen & External”.
It is at least an unusual revelation, because otherwise we would expect the calculation star to be made on a single process. But with no further comment from Intel offered, make that what you will. Maybe they will be simple, and will they actually use two very different process nodes for the calculation?
