One per vs. Core Performance Balance

Section by Ian Cuttres

Advent of AMD 3^R.D. Generation EPYC processor family is expected using the new Zen3 core. The promise of a new processor core microarchitecture, updates in connectivity, and new security options while maintaining platform compatibility is a good step to enterprise platform update, but one true metric is platform performance. Expectations of a similar slam-dunk in the enterprise market increased as the Zen 3 score led to the final counter-main performance in the previous consumer market in November, and today we will see those results.

AMD EPYC 7003: 64 cores of Milan

AMD is promoting headline numbers with the new pay generation of hardware due to enhancements with the new core design, which is 19% in raw performance throughput. On top of this, AMD has new security features, optimized optimization for various memory configurations, and an updated display with endless fabric and connectivity.

3rd General EPYC

Looking for abbreviated specifications on the new EPYC 7003 series, known by its codename Milan, it will see a lot of familiarity with the previous pay-per-view, although this time around targeting various design points around AMD.

Milan processors will deliver 64 cores and 128 threads using AMD’s latest Zen 3 cores. The processor, like the ROM, is designed with eight chipsets of eight cores, but this time all eight cores of the chiplet are connected, enabling an effective double L3 cache design for the lower overall cache latency structure. All processors will have 128 lanes of PCI 4.0, eight channels of memory, with most models supporting dual processor connectivity, and new options for channel memory optimization available. All Milan processors must be compatible with ROM series platforms with firmware updates.

AMD EPYC: Generation on Generation
AnandTech	EPYC Held at 7001	EPYC Is 7002	EPYC Held at 7003
Code name	Naples	Rome	Milan
Microarchitecture	Zen	Zen 2	Zen 3
Core manufacturing	14 nm	7nm	7nm
Maximum cores / threads	32/64	64/128	64/128
Core complex	4C + 8MB	4C + 16MB	8C + 32MB
Memory support	8x DDR4-2666	8 x DDR 4-3200	8 x DDR 4-3200
Memory capacity	2 TB	4 TB	4 TB
PCI	3.0 x128	4.0 x128	4.0 x128
Security	SME SEV	SME SEV	SME SEV SNP
Peak power	180 W.	240 W *	280 W.
* Rome introduced the special HPC 280 W for mid-cycle

One feature here is that the new Pay Generation processors will offer 280W models to all customers – there were only 240W models for all previous Pay Generations and then 280W for certain HPC customers, although at the moment all customers can enable that high performance. Parts with core design.

This is an example if we compare the direct top-f-stack processor:

2p Top Stf Stack GA2 Furings
AnandTech	EPYC Held at 7001	EPYC Is 7002	EPYC Held at 7003		Intel Keon
Processor	Held at 7601	Is 7742	Held at 7763		6258 r
uArch	Zen	Zen 2	Zen 3		Cascade
Coro	32	64	64		28
TDP	180 W.	240 W.	280 W.		205 w
Base freak	Is 2200	Is 2250	Is 2450		2700
Turbo Freak	3200	3400	Is 3500		Is 4000
L3 Cash	64 MB	256 MB	256 MB		37.5 MB
PCI	3.0 x128	4.0 x128	4.0 x128		3.0 x48
DDR4	8 x 2666	8 x 3200	8 x 3200		6 x 2933
DRAM CAP	2 TB	4 TB	4 TB		1 TB
Price	00 4200	50 6950	90 7890		50 3950

The new top processor for AMD is the EPYC 7763, a 64-core processor at 280 W TDP, with a 2.45 GHz base frequency and a 3.50 GHz boost frequency. AMD claims that this processor offers 106% performance in the industry benchmark compared to Intel’s best 2P28-core processor, the Gold 6258R and its previous pay generation 280W version 7H12.

Peak Performance vs. Core Performance

One of AMD’s goals with the new Milan Pay is to become a performance metric, the company not only runs after ‘peak’ numbers, but also for software, taking a more comprehensive view of customers, especially for software that has always been an all-major performance. Limited or licensed. With that in mind, AMD’s F-Series of ‘fast’ processors are now being crystallized in the stack.

AMD EPYC 7003F series processors
	Coro Threads	Foundation Freak	Turbo Freak	L3 (MB)	TDP (W)	Price
F Series
EPYC 75F3	32/64	2950	Is 4000	256 (8 x 32)	280 W.	60 4860
EPYC 74F3	24/48	3200	Is 4000		240 W.	00 2900
EPYC 73F3	16/32	Is 3500	Is 4000		240 W.	21 3521
EPYC 72F3	8/16	Is 3700	Is 4100		180 W.	68 2468

These processors have peak single threaded values ​​of anything else in AMD’s offering fur, along with a full 256MB L3 cache, and our results get the best scores based on each thread more than anything we’ve tested for Enterprise in x86. And Arm – more details in the review. F series processors will come a little more premium than others.

AMD EPYC: Tour of Italy

The first pay generation of EPYC was launched in June 2017. At the time, AMD was essentially a phoenix: emerging from the ashes of its previous Optron business, and with a promise to return to high-performance computing with a new processor design philosophy.

At the time, traditional enterprise customer support was not initially assured – AMD’s last push into the enterprise space with a new pay-generation paradigm-shifting processor core was a success when it flattened out as AMD had to prevent itself from going bankrupt. Optron customers had no updates at the time, and there was no positive prospect for many for wanting to jump on the unfamiliar platform of a company that had sunk in the past.

At the time, AMD had laid out a three-year roadmap, detailing its future pay generations and the roadmap for the company to reach 99% market share in performance and ingings. These were seen as goals, and many people sat back and watched gambling.

1st General EPYC launch

As the first pay generation Naples were launched, it offered some impressive display numbers. It didn’t compete fairly well in all areas, and with any new platform, there were going to be some jagged issues to start with. Before AMDA gradually expanded the ecosystem, it kept an initial cycle for some of its key OEM partners. Naples offers a comprehensive PCI. and was the first platform to provide a lot of memory support, and the platform initially aimed at storage or PCI heavy deployments.

2nd General EPYC launch

Generation Gust of the second pay generation launched in August 2019 (+26 months) generated more fanfare. AMD’s latest Zen 2 core was competitive in consumer space, and there were many key design changes to the SOC layout (such as moving to ALA flat design) that encouraged many skeptics to start evaluating the platform. It was of such interest that AMDA told us that they should be selective with which OEM platform they were going to assist before launching the OEM facial. Rome’s performance was good, and it won a few high-profile supercomputers, but more importantly, it was able to implement the AMD roadmap in June 2017.

With its flat SOC architecture, updated Zen2 processor core (which actually borrows elements from Zen3) and PCI 4.0, AMDA allowed performance to start competing only on Io, and AMD’s OEM partners were constantly announcing ROM processors. . As a compute platform, there are often higher Intel memory support and more PCI inings fringes by replacing two Intel 28-core processors for an AMD 64-core processor. This also allows computational density, and AMD was in a position where it could help implement software optimization for its platform, perform, but also move toward equality on edge cases for which its competitors were highly optimized. All major hyperscalers evaluated and deployed internal as well as AMD based offerings for their clients. AMD’s approval sticker was there too.

3rd Gen EPYC CPU

And so today AMD continues that tour of Italy with a trip to Milan some 19 months after Rome. The built-in SOC layout is similar to ROM, but we have higher performance on the table, with extra security and more configuration options. Hyperscalers are already getting the final hardware for their deployment for six months, and AMD is now in a position to help enable more OEM platforms at launch time. Milan is compatible with ROM, which definitely helps, but with Milan covering more optimization points, AMD believes it is in a better position to target the market with high-performance processors and high-per-core performance processors. Before.

AMD sees Milan’s launch as the third step in the roadmap it showed in June 2017, and recognizes its ability to execute reliably for its customers but also offers industry-standard performance benefits to its customers.

The next stop on the tour of Italy is Genoa, which is set to use AMD’s upcoming Zen4 microarchitecture. AMDA has also said that the Zen5 is in the pipeline.

Competition

AMD will unveil this new pay generation of Milan processors approximately 19 months after the unveiling of the Rome. In that time we’ve seen the launch of both the Amazon Graviton 2 and the Ampere Ultra, built on cores at Arm’s Neover N1 family.

Milan top-of-the-stack competition
AnandTech	EPYC Held at 7003	Amazon Graviton 2	Ampere Ultra	Intel Keon
Platform	Milan	Graviton 2	QuickSilver	Cascade
Processor	Held at 7763	Graviton 2	Q80-33	6258 r
uArch	Zen 3	N1	N1	Cascade
Coro	64	64	80	28
TDP	280 W.	?	250 W.	205 w
Base freak	Is 2450	Is 2500	Is 3300	2700
Turbo Freak	Is 3500	Is 2500	Is 3300	Is 4000
L3 Cash	256 MB	32 MB	32 MB	37.5 MB
PCI	4.0 x128	?	4.0 x128	3.0 x48
DDR4	8 x 3200	8 x 3200	8 x 3200	6 x 2933
DRAM cap	4 TB	?	4 TB	1 TB
Price	90 7890	N / A	50 4050	50 3950

From Intel, the company has divided its efforts between large socket and small socket configurations. Cooper Lake is for larger sockets (4+), a Skylake derivative for select customers only. For smaller socket configurations (1-2), Intel will launch its 10nm Ice Lake portfolio this year, but so far it has remained silent on a specific date. For that purpose, all we have to compare Milan to is Intel’s Cascade Lake Xion scalable platform, which was the same platform as Rome.

Interesting time for sure.

This review

For this review, AMDA gave us remote gave access to many similar servers with different processor configurations. We focused our efforts on top-of-the-stack EPYC 7763, 280W 64-core processor, EPYC 7713, 225W 64-core processor, and EPYC 7F53, a 280W 32-core processor. Halo Milan processor for per core performance.

On the next page we will go to AMD’s Milan processor stack, and compare its ROM as well as the current Intel Ings fur. We then go through our testing systems, test our SOC structure (cache, core-to-core, bandwidth), processor power and then discuss our full benchmark.

1. This page, observation
2. Milan processor er ferings
3. Bed setups, compiler options
4. Topology, memory subsystem and latency
5. Processor Power: Core vs. Io
6. Spec: Multi-thread performance
7. Spec: Single-thread performance
8. Spec: Win Per Core Performance for 75F3
9. SpecJBB MultiJVM: Java Performance
10. Coordinate and calculate benchmarks
11. Conclusions and final comments

These pages can be accessed by clicking the links or by using the drop down menu below.