The latest benchmarks from Intel’s next-generation Ice Lake-SP Xeon CPU server family have been leaked and show some interesting results compared to current-generation AMD EPYC Rome third-generation CPUs.
Intel’s next-generation 10nm Ice Lake-SP CPUs tested, two chips with 28 cores and 56 threads each against a single flagship AMD EPYC Rome 64 Core
As part of the Whitley platform, the Intel Ice Lake-SP CPU line will be comprised of multiple Xeon chips. We have already seen 6 cores and 24 main parts, but the last one is a 28 core part and has been detected by TUM_APISAK in Geekbench database and Momomo_US also in SiSoftware database.
The Intel Ice Lake-SP CPU was tested on a dual socket server and has two of the chips. Each chip features 28 cores and 56 threads that round up to 56 cores and 112 threads in total. Since the chip is still an early engineering sample, it features lower clock speeds of 1.5 GHz base and boost clocks up to 3.20 GHz. The CPU features 42 MB of L3 cache and 35 MB of L2 cache for a total of 77 MB cache. The Ice Lake-SP 2S server was equipped with 512GB of memory that should sync at 3200MHz and was presented in an 8-channel configuration, which is one of the highlights of the new Whitley platform.
The performance of the 2S Intel Ice Lake-SP server was evaluated in Geekbench 4, which benefits from the AVX-512 instruction set introduced in Intel’s current and future Xeon CPU families. In single-core tests, the server scored up to 3,443 points, and in multi-core tests, the chip scored up to 37,317 points.
Before comparing it to the AMD EPYC 7742, it should be noted that both test results are based on early engineering samples with lower clock speeds, so the final performance is expected to be much better. At the same time, however, Intel CPUs benefit from this benchmark from their AVX-512 instruction set that AMD CPUs lack. Entries are also displayed in different operating system environments, although the EPYC 7742 CPU was indeed tested in a Windows 10 server configuration, Geekbench does not report correctly. Regardless of that, let’s see how the two 28-core Ice Lake-SP Xeon CPUs stack on a single AMD EPYC 7742 CPU.
We used a single EPYC 7742 input for comparison, so we’re comparing a total of 64 cores and 128 threads from AMD with 56 cores and 112 threads from Intel. The AMD EPYC 7742 CPU easily outperforms the Intel chips in single-core tests, due to the higher base clock speeds of 3.4 GHz versus 1.5 GHz in the Intel parts. At the same time, the AMD platform offers around 35,000 multicore points that are slightly lower than parts of the Intel Ice Lake-SP. At the ultimate clock speeds, Ice Lake-SP CPUs can easily outperform AMD EPYC Rome parts, but the advantage may not be as great as Intel had hoped.
Obviously, it seems that Intel’s Ice Lake-SP was more of a competitor to EPYC Roma that missed its initial schedule due to low 10nm performances and now has to compete against AMD’s EPYC Milan just around the corner . We’ll wait to see more test and performance results for Ice Lake-SP CPUs on optimized non-AVX 512 workloads, but every benchmark leak makes it very clear that Ice Lake-SP is late and AMD is not going to make things better for Intel
And it’s not just about performance metrics either, we still don’t know the prices and energy efficiency of Ice Lake-SP, but we do know that the existing line of EPYC Rome has much lower prices and TCO than Cascade Lake- The lineup from SP and is expected to remain intact even when Ice Lake-SP is shipped.
Intel Xeon SP families:
| Family brand | Skylake-SP | Cascade Lake-SP / AP | Cooper Lake-SP | Ice Lake-SP | Sapphire Rapids | Granite rapids |
|---|---|---|---|---|---|---|
| Process node | 14nm + | 14nm ++ | 14nm ++ | 10nm + | 10nm ++ | 7nm +? |
| Platform name | Intel Purley | Intel Purley | Intel Cedar Island | Intel Whitley | Intel Eagle Stream | Intel Eagle Stream |
| MCP SKU (multi-chip package) | Not | yes | Not | yes | TBD | TBD |
| Plug | LGA 3647 | LGA 3647 BGA 5903 |
LGA 4189 | LGA 4189 | LGA 4677 | LGA 4677 |
| Max Core Count | Up to 28 | Up to 28 Up to 48 |
Up to 28 | Up to 56? | TBD | TBD |
| Maximum thread count | Up to 56 | Up to 56 Up to 96 |
Up to 56 | Up to 112? | TBD | TBD |
| Max L3 cache | 38.5 MB L3 | 38.5 MB L3 66 MB L3 |
38.5 MB L3 | TBA (1.5 MB per core) | TBD | TBD |
| Memory support | 6 channel DDR4-2666 | DDR4-2933 6 channels DDR4 2933 12-channel |
Up to 6 DDR4-3200 channels | Up to 8 DDR4-3200 channels | 8 channel DDR5 | 8 channel DDR5 |
| PCIe Gen Support | PCIe 3.0 (48 lanes) | PCIe 3.0 (48 lanes) | PCIe 3.0 (48 lanes) | PCIe 4.0 (64 lanes) | PCIe 5.0 | PCIe 5.0 |
| TDP range | 140W-205W | 165W-205W | 150W-250W | ~ 250W- ~ 300W | TBD | TBD |
| 3D Xpoint Optane DIMM | N / A | Apache Pass | Barlow Pass | Barlow Pass | Crow pass | Donahue Pass |
| Competition | AMD EPYC Naples 14nm | AMD EPYC Roma 7nm | AMD EPYC Roma 7nm | AMD EPYC Milan 7nm + | AMD EPYC Genoa ~ 5nm | EPDC AMD Next-Gen (Post Genoa) |
| Launching | 2017 | 2018 | 2020 | 2020 | 2021 | 2022-2023? |
Intel Xeon 10nm + Ice Lake-SP family
Intel Ice Lake-SP processors will ship later this year and will be based on the 10nm + process node. We’ve seen previous slides that say the Ice Lake family would feature up to 28 cores, but the one from the ASUS presentation says it would actually feature up to 38 cores and 76 threads per socket. There are also rumors indicating as many as 56 cores and 112 threads, so we can’t say for sure what the actual cores will look like on the new chips.
The highlight of the Ice Lake-SP processors will be support for PCIe Gen 4 and 8-channel DDR4 memory. The Ice Lake Xeon family would offer up to 64 PCIe Gen 4 lanes and offer support for 8 channel DDR4 memory with 3200 MHz clock speed (16 DIMMs per socket with second generation persistent memory support). Intel Ice Lake Xeon processors would be based on the new Sunny Cove core architecture offering an 18% improvement in IPC compared to the Skylake core architecture that has been in place since 2015.
One thing to note is that Intel’s 10nm by 2020 is an improved node from the original 10nm node that will mark its debut with Tiger Lake CPUs. It’s marked as 10nm + and that’s specifically what the Ice Lake-SP Xeon line will use. Some of the main updates that 10nm will deliver include:
- Density scale 2.7x vs 14nm
- Self-aligning quad patterns
- Contact on active door
- Cobalt interconnect (M0, M1)
- First-generation 3D stacking Foveros
- 2nd Gen EMIB
The Intel Ice Lake-SP line would compete directly against AMD’s upgraded 7nm EPYC Milan line, which will feature the new 7nm Zen 3 core architecture, which is confirmed to be one of AMD’s biggest architectural updates since the Zen core. original. Expect to see more Intel and NVIDIA based servers in the coming months.
