The 2nd generation Intel Xeon Scalable platform provides the basis for a powerful data center platform that makes a leap in maneuverability and scalability. Intel Corporation on April 2, 2019 introduced a portfolio of data-centric tools to help its customers gain more value from their data. (Credit: Intel Corporation)
Intel has revealed the details of its next generation Xeon CPU family nickname Ice Lake-SP at HotChips 32. Later this year, Ice Lake-SP will host CPUs for a range of new features, such as a brand new chip architecture, improved I / O, and an improved software stack with Intel’s first 10nm server setup.
Intel Ice Lake-SP ‘Next-Gen Xeon’ CPUs Detailed – Feature 10nm + Sunny Cove Cores and Advanced Features
The Intel Ice Lake SP will officially launch later this year on the Whitley platform. The platform will scale to server and dual-socket servers. In its presentation, Intel unveiled a 28-core Ice Lake-SP CPU as an example to demonstrate the enhanced capabilities that Ice Lake-SP offers over Cascade Lake-SP.
Intel has not confirmed if the 28-core CPU they have displayed is the highest core count available with the Ice Lake SP family or if there would be higher variants of core counts. Earlier rumors point to higher core counts, so this 28 core star could just be used for comparison with the top of the stack of 2nd Gen Xeon CPUs available today.
CPU Ice Architecture from Intel Ice Lake-SP ‘Next-Gen CPU’
Coming to the details, Intel states that its Ice Lake SP CPUs are manufactured on the 10nm + process and not the 10nm ++ process used by the Tiger Lake CPUs launching next month. The Ice Lake SP family will take advantage of the Sunny Cove cores that provide up to 18% IPC increase over the Skylake architecture used by all 14nm Xeon CPUs.
Intel’s 3rd Gen Xeon Scalable Family, Codenamed Ice Lake-SP, Presentation at HotChip 32 (Image Credit: HardwareLuxx)
The Sunny Cove architecture generally adds a variety of improvements over Cascade Lake as well as the improved Skylake cores such as:
- Improved frontend: higher capacity and improved branch predictor
- Wider and deeper machine: wider allocation and execution resources + larger structures
- Improvements in TLBs, single thread implementation, prefetching
- Server Enhancements – Larger Mid-level Cache (L2) + Second FMA
Intel is also adding a variety of new SIMD instructions exclusively for the Sunny Cove server processors that are primarily designed to increase performance in Cryptography and compression / decompression workloads. That along with improved software and algorithmic support will allow Intel gains of up to 8X per core across Cascade Lake.
Intel Xeon SP Families:
| Family Branding | Skylake-SP | Cascade Lake-SP / AP | Cooper Lake-SP | Ice Lake-SP | Sapphire Rapids | Granite Rapids |
|---|---|---|---|---|---|---|
| Node processing | 14nm + | 14nm ++ | 14nm ++ | 10nm + | 10nm ++ | 7nm +? |
| Platform Name | Intel Purley | Intel Purley | Intel Cedar Island | Intel Whitley | Intel Eagle Stream | Intel Eagle Stream |
| MCP (Multi-Chip Package) SKUs | no | Yes | no | Yes | TBD | TBD |
| Socket | LGA 3647 | LGA 3647 BGA 5903 |
LGA 4189 | LGA 4189 | LGA 4677 | LGA 4677 |
| Maximum core count | Until 28 | Until 28 Up to 48 |
Until 28 | TBD | TBD | TBD |
| Maximum thread count | Up to 56 | Up to 56 Up to 96 |
Up to 56 | TBD | TBD | TBD |
| Max L3 Cache | 38.5 MB L3 | 38.5 MB L3 66 MB L3 |
38.5 MB L3 | TBA (1.5 MB per core) | TBD | TBD |
| Memory support | DDR4-2666 6-channel | DDR4-2933 6-channel DDR4 2933 12-channel |
Up to 6-channel DDR4-3200 | Up to 8-channel DDR4-3200 | 8-channel DDR5 | 8-channel DDR5 |
| PCIe Gen Support | PCIe 3.0 (48 lanes) | PCIe 3.0 (48 lanes) | PCIe 3.0 (48 lanes) | PCIe 4.0 (64 lanes) | PCIe 5.0 | PCIe 5.0 |
| TDP range | 140W-205W | 165W-205W | 150W-250W | ~ 250W- ~ 300W | TBD | TBD |
| 3D Xpoint Optane DIMM | N / A | Apache Pass | Barlow Pass | Barlow Pass | Crow Pass | Donahue Pass |
| Competition | AMD EPYC Naples 14nm | AMD EPYC Rome 7nm | AMD EPYC Rome 7nm | AMD EPYC Milan 7nm + | AMD EPYC Genoa ~ 5nm | AMD Next-Gen EPYC (Post Genoa) |
| Start | 2017 | 2018 | 2020 | 2020 | 2021 | 2022-2023? |
Intel Ice Lake-SP ‘Next-Gen CPU’ 28 Core Die & Whitley platform detailed
Looking at the block diagram of the Ice Lake-SP 28-core CPU, the chip offers a new interconnect in the form of an improved Mesh Fabric that runs through all 28 CPU cores. The Ice Lake-SP die has two 4-channel memory controllers, while the Cascade Lake-SP die offers two tri-channel memory controllers.
The Intel Ice Lake SP Processors also have four PCIe Gen 4 controllers, each offering 16 Gen 4 routers for a total of 64 routers on the 28 core drives. The Cascade Lake SP chips will offer hexa-channel memory support, while Ice Lake-SP will offer octa-channel memory support on the Whitley platform at launch. The platform will be able to support up to DDR4-3200 MHz memory (16 DIMMs per socket with 2nd Gen continuous memory support).
Intel also adds a range of latency and coherence optimizations to Ice Lake SP chips. But you can see that the memory bandwidth latency gets a big jump with the 8-channel memory interface and the higher DIMM speeds.
Intel Ice Lake-SP ‘Next-Gen CPU’ New interconnect infrastructure
In addition to the standard Mesh interconnect, Intel has further expanded its interconnect design for Ice Lake-SP Xeon CPUs. The new control material and data material wants to connect to the cores and various controllers of the chip, but also manage the data flow and power control for the chips themselves. These new interconnects deliver even lower latency and faster clock updates than 3rd Gen Cooper Lake SP chips. For example, the core frequency transition takes 12us and the mesh frequency transition takes 20us on Cascade Lake SP chips. Ice Lake-SP in comparison takes less than 1us and 7us, respectively.
The lower frequency train means higher efficiency across Cascade Lake. Ice Lake-SP will also improve on AVX frequency, as not all AVX-512 workloads consume higher power. This is also not specific to AVX-512 alone. Even AVX-256 instructions on Ice Lake-SP will provide better frequency profile over Cascade Lake CPUs.
Some of the major upgrades that 10nm will deliver include:
- Scaling of 2.7x vs 14nm
- Self-tuned Quad-Patterning
- Contact over active port
- Cobalt Interconnect (M0, M1)
- 1st Gen Foveros 3D Stacking
- 2nd Gen EMIB
The Intel Ice Lake-SP lineup would compete directly with AMD’s improved 7nm-based EPYC Milan lineup, which will feature the brand new 7nm Zen 3 core architecture, which is confirmed as one of AMD’s biggest architectural upgrade since the original Zen core. Expect to see more Intel & NVIDIA based servers in the coming months.
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