This Tuesday, Intel held an all-day virtual ‘Architecture Day’ conference and took participants on a deep dive into the architecture of upcoming products in all categories: CPUs, GPUs (dedicated and integrated), and FPGAs. We learned a lot about what Intel’s worked on and why, with the most concrete details about the most difficult release – Tiger Lake’s new laptop processors from next month.
Dig the ticks, the teeth and the pluses
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“Be faster with everything, without using more power” is a pretty solid goal for a laptop CPU architecture.
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IBM’s Raja Koduri tells us about a transition from transistor-coupled to “transistor-elastic” design – meaning the ability to carry functions from one process node to the next.
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Intel is making a case that its 10nm architecture is worth the wait because it delivers more than simple density.
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We don’t often see CPU manufacturers talking about individual transistors – but Intel has spent much of the day doing just that.
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Intel says its new capacitors hold significantly more charge, while offering significantly less resistance – and thus better energy efficiency, with less heat.
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Intel combines its SuperMIM and Redefined FinFET technology buzzwords into a single buzzword to close the ++ terminology, calling the new process at Tiger Lake “SuperFin.”
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Even for a conference called “Architecture Day”, Intel took us unusually deep into its manufacturing processes and packaging. The presentations of the day focused as much on improvements in the individual transistors and capacitors as on improvements in the processor designs themselves.
In addition to the purely educational angle, Intel’s focus on the lower levels of design appeared to serve two purposes. The focus on the lower level made Intel’s 10nm process sound worth the unexpectedly long wait – and it gave Intel the chance to dig the weird “++” backlinks to its process size and the whole thing a more human-friendly “SuperFin “to call.
With the 14nm process hitting “++++” and the 10nm already on “++”, even Intel’s own engineers began to get confused when talking to each other. That change is good for more than just marketing. The name SuperFin is a portmanteau of “SuperMIM capacitor design” and “FinFET transistors redesigned.”
From micro to macro
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Willow Cove, the architecture Tiger Lake is built on, offers more cache, new security features, and significantly higher clock frequencies than Ice Lake.
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As voltage increases, so does maximum clock speed. The Willow Cove architecture allows both lower and higher voltages than Sunny Cove did – and higher clocks can boot at the same voltages.
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Say goodbye to “Iris” and “Iris +”, and say hello to Xe. Specifically, Xe LP – presumably Low Power – is the iGPU architecture in Tiger Lake.
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Tiger Lake starts with LP-DDR4 support, but will eventually also support LP-DDR5 RAM.
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Tiger Lake offers a more efficient Gaussian and Neural Accelerator, used for very low inference tasks for power.
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Tiger Lake will have the ability to drive more, higher-resolution screens than Ice Lake – and consume higher-resolution image for AI workloads via its IPU6 pipeline, too.
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The problem with talking about the quality of individual transistors and capacitors in a general package is that it is difficult to translate directly to performance. So now that we know that Intel has worked hard at the lower levels, we move on to design principles that are a little more familiar to most – voltages, frequencies, and subprocessors.
Tiger Lake is built on Willow Cove, the micro-architecture that follows Ice Lake’s Sunny Cove. Willow Cove is billed as a major improvement over Sunny Cove bypass, with added security features, higher cache, and significantly improved clock speeds.
The added clock speed of Willow Cove does not come with a handicap for power consumption. Willow Cove processors have both greater dynamic range and higher efficiency than the Sunny Cove Processors did – they can operate at both lower and higher voltages, and their frequencies (any scale with voltage) are also higher at the same voltage.
We are also looking forward to enormously improved integrated graphics. Ice Lake’s Iris + was a necessary shot in the arm for Intel’s traditionally wimpy iGPUs, but it still lagged significantly behind AMD’s Vega 11 integrated laptop graphics. Tiger Lake removes Iris + and introduces the much spotty Xe LP instead.
Intel describes its new line of Xe graphics, including Xe LP, as “industry-leading” – and although the company does not yet speak public benchmarks, we do not think it is a joke. Benchmarks for Leaked Time Spy show a Tiger Lake i7-1165G7 beating AMD’s Ryzen 7 4700U on GPUs by a significant margin – 35 percent of the raw score.
The same leaked benchmarks have the quad-core / eight-thread i7-1165G7 and the 8c / 8t Ryzen 7 4700U in a dead heat for CPU capability, with effectively distinguishable scores. It is worth noting here that Time Spy is notoriously thread-limited – despite the fact that the Ryzen 7 4800U, with eight cores and 16 threads, beats the CPU score of i7-1165G7 by 34 percent.
Eventually, Tiger Lake will be able to drive more images at higher resolutions – and manage AI workloads on higher resolution pipelines – than Ice Lake could.
Conclusions
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The TL; DR with all micro-level enhancements is a performance of the same node as large or greater than a full node shrinkage.
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Intel is clearly well aware of the “meh” reaction on Ice Lake – and promised Tiger Lake will be all but more of the same.
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The microarchitecture that will succeed Willow Cove this year is next year’s Golden Cove – which will also come with a low-power micro-architecture (Atom / Celeron) called Gracemont, and a hybrid called Alder Lake.
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We have not actually got our hands on all of Tiger Lake components, and there is a world of difference between manufacturers’ claims and fully realized, independently tested systems. But Intel oozes virtually renewed confidence and makes bold, if early, claims. It seems like a safe bet that Tiger Lake laptop CPUs will be serious competition for AMD’s Ryzen 4000 – which neither Ice Lake nor Comet Lake really were.
The really interesting question – and one of which Intel is still becoming cagey – is how many Tiger Lake CPUs Intel is capable of supplying to OEMs. The company’s presenters said the problems with the 10nm supply we saw in Ice Lake had been “overcome” – but they did not give much definition of what that meant.
As we pushed Intel drivers further, we received confirmation that there would be no recurrence of Comet Lake – the 11th generation mobile parts will only be 10nm, with no competing 14nm announcement. But that statement came with some remarkably cautious hedges about what OEMs choose to buy and for how long. This could just be caution, or it could be an indication that Tiger Lake will only be seen in relatively low volume, high end systems in much the same way as Ice Lake was.
