By Stephen Nellis
(Reuters) – Intel Corp
The company Santa Clara, in California, is one of the few left in the world that both designs and produces its own chips. But its manufacturing companies have become a concern among investors after Intel said last month that its next-generation chip-making process, called its 7-nanometer process node, would be delayed.
Analysts believe the delays could cement the lead that rivals such as Taiwan Semiconductor Manufacturing Co. <2330.TW> have won in making smaller, more efficient chips. Intel shares have fallen nearly 20% since the delays were announced.
On Thursday, Intel tried to dispel the idea that the names of one number given to each generation of chip process node tell the whole story by revealing improvements to its existing 10-nanometer process node. It announced a new way to make what it now calls “SuperFin” transistors, which, along with a new material used to upgrade the capacitors on chips, are expected to improve the performance of future Intel processors improve, even though they are still being made at 10 -Nanonmeter production line.
“It’s 20%, the biggest jump within node in our history,” said Raja Koduri, Intel’s chief architect, of performance gain in an interview with Reuters. “It’s actually the same as what you would get with one full Moore’s Law node of performance.”
It will not be possible to test those claims in the real world until Intel’s new chips come out, but their “Tiger Lake” laptop chips shelf for release this fall will use the chips.
Even with the new transistor technology, Koduri said that Intel has revamped its chip design process to make it easier to use both its own chip factories and outside chip factories, which is necessary to make the best chips.
“Whatever makes us deliver these products on time, with leadership performance, we have the flexibility and will use that,” he said.
(Report by Stephen Nellis in San Francisco; Edited by Leslie Adler)
